(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a logic circuit using a Schottky junction type field effect transistor formed on a gallium arsenide (GaAs) substrate.
(2) Description of Related Art
In a semiconductor integrated circuit device equipped with an input circuit formed on a semiconductor substrate, which circuit has an input logic level conversion circuit using field effect transistors (hereinafter referred to as "FET"s) and diode, the matching between the levels of the external input signal and the logic levels of the internal logic circuit is achieved by making the output voltage of the input logic level conversion circuit to be always identical with the input logical threshold value of the internal logic circuit connected to the input logic level conversion circuit, whereby the stability of the circuit against fluctuations in the power source voltage and changes in temperature is achieved.
Conventionally, in the semiconductor integrated circuit device of the kind explained above (hereinafter called "GaAs IC"s), a single-ended type logic circuit is widely used because of the simplicity of its circuit configuration and its comparative ease in securing a wide circuit operation margin due to a high voltage gain.
Typical circuits are shown in FIG. 1A and FIG. 1B. An internal logic circuit 9 shown in FIG. 1A is called "DCFL" (abbreviation of Direct Coupled FET Logic circuit), and consists of a load FET Q1a of a depletion mode and a driving FET Q2a of an enhancement mode. Also, an internal logic circuit 9B shown in FIG. 1B is called "BFL" (abbreviation of Buffered FET Logic circuit), and consists of a level shift diode D2 and FETs Q1b, Q2a, Q3a and Q4a, all being of a depletion mode and having the same threshold voltage.
As it is normal that the internal logic levels of the GaAs IC and the external logic levels are not identical, an input logic level conversion circuit 10A should be provided. The ECL levels are generally used for the high-speed digital signal processing system. Therefore, in the above circuits, the power supply voltage V.sub.DD is set at the voltage of ground potential, the first source power supply voltage V.sub.SS1 is set at V.sub.SS1 =-2 V and the second source power supply voltage V.sub.SS2 is set at V.sub.SS2 =-5.2 V.
The level matching between the logic levels in the internal logic circuit in the GaAs IC and the external logic levels is indispensable for realizing an ultra-high speed operation in the GaAs ICs. Especially, in the ECL levels, it is 0.7.about.0.8 V between the peaks of logic amplitudes. Consequently, level matching errors tolerable in the above level matching must be suppressed within a range of .+-. (100.about.200) mV. In other words, the input logic level conversion circuit must have some kind of adjusting function in order to hold the necessary logic level matching against fluctuations in the power supply voltages or changes in the device parameters due to temperature changes.
However, the input logic level conversion circuit 10A in FIGS. 1A and 1B does not have such a function, and has the problems, for instance, that the tolerable range of fluctuations in the first source power supply voltage V.sub.SS1 is less than .+-. (100.about.150) mV, and that it is also weak against temperature changes because of the temperature dependency (about -1 mV/.degree.C.) of the level shift amount V.sub.F of the level shift diode D1. Especially, in the ultra high-speed region of more than several Gbps, the maximum operation speed of the GaAs IC is determined in many cases by the properties of level matching of the input logic level conversion circuit and this was a problem. Also, in the large scale integrated circuit (LSI), generally, it is a trend to try to improve the FET performance and to decrease the logic amplitude in order to achieve low power consumption and high speed operation at the same time. In this case, the above problem of level matching becomes especially conspicuous and becomes a big barrier to the actual usage of the GaAs ICs.
On the other hand, in the BFL circuit shown in FIG. 1B, the logical threshold value of the BFL inverter is equal to the first source power supply voltage V.sub.SS1 in the case where the gate width, the threshold voltage, etc. of the FET Q1b are the same as those of the FET Q2a. In this case, although a change in the logic threshold value due to a temperature change is eliminated, the above mentioned problem as to the level matching is not solved because of the temperature dependency of the level shift diode D1. The input logic level conversion circuit which has an adjusting function on the above temperature properties of the level shift amount V.sub.F of the level shift diode D1 and the changes in the first source power supply voltage V.sub.SS1 is proposed in the Japanese Patent Application Kokai No. 32,112/1991 (Hei 3-32,112).
The input logic level conversion circuit mentioned above is shown in FIG. 2 with a reference numeral 10. By applying the condition of the following equation (1) to the number of each diode group n1.about.n3, N2 and N3, the internal output voltage V3 can be expressed by the equation (2). EQU n1+(N2-n2)-(N3-n3)=0 (1) EQU V3=V.sub.SS1 +(V.sub.IN1 -V.sub.REF) (2)
Here, when the level of the input signal voltage V.sub.IN applied to an input terminal 18 is equal to the reference signal voltage V.sub.REF applied to a reference input terminal 17, the internal output voltage V3 derived from an output node 16 becomes equal to the first source power supply voltage V.sub.SS1 supplied to a first source power supply terminal 12. By connecting an internal logic circuit 9B to the above input logic level conversion circuit 10, which is a BFL circuit in which the gate width of the FET Q1b is set equal to that of the FET Q2a, it is made possible to achieve full compensation and adjustment on the matching error of input logic level, caused by the fluctuations in the first source power supply voltage V.sub.SS1 and the temperature change, whereby the maximum operation speed is improved, the usable temperature range is enlarged and the tolerance range for the power supply voltages in the GaAs ICs is enlarged.
However, for the internal logic circuit in which the threshold value of the input logic is not equal to the first source power supply voltage V.sub.SS1 such as the DCFL circuit shown in FIG. 1A and a more typical BFL circuit in which the gate width of the FET Q1b is not equal to that of the FET Q2a, even by the input logic level conversion circuit 10, the above mentioned compensation function is insufficient, and this has been a problem because the matching error caused by the power supply voltage fluctuations and the temperature dependency remains unadjustable.
Therefore, in order to realize a high integration density and a high-speed operation, in the input circuit of the GaAs IC which consists of the logic circuit of the single-ended type, it is necessary to have the function of compensation and adjustment so as to keep a sufficient level matching between the external logic level and the logic level of the internal logic circuit against the factors such as changes in the fluctuations of the source power supply voltage (V.sub.SS1) and changes in the temperature or the changes in the device parameters, regardless of the types of internal logic circuits.
In the conventional semiconductor integrated circuit devices as explained above, however, there was no input circuit that has the aforementioned compensation and adjusting function for the combinations with all kinds of internal logic circuits, and there was no circuit to improve and increase resistance to the matching error.